EnggViz
▶ Launch IDE

Free · Browser-Based · No Install · No Account

Engineering Education,
Built for Depth

EnggViz is a free platform for engineering students and professionals — combining an interactive concept visualizer, a professional Verilog IDE, and a technical blog into one coherent learning ecosystem.

▶ Open RTL Lab Explore Platform
3
Platform Tools
16
ECV Visualizations
6
IDE Integrations
Free
Always

The Platform

The EnggViz Ecosystem

ECV · enggviz.online
Engineering Concept Visualizer

Transform abstract engineering theory into interactive, real-time visualizations. Explore how systems actually behave — from Bode plots and root locus to pipelined CPUs and VLSI layouts — without solving equations on paper first.

Control Systems Signal Processing Computer Architecture VLSI 16 Modules
Explore Visualizations → RTL Lab · lab.enggviz.online
Online Verilog IDE

A professional-grade Verilog and SystemVerilog IDE running entirely in the browser. Simulate with Icarus Verilog, synthesize RTL schematics with Yosys, inspect waveforms, extract FSMs, and get AI-powered hardware assistance — all in one tab.

Icarus Verilog Yosys RTL WaveDrom AI Copilot No Install
Launch IDE → Blog · blog.enggviz.online
Technical Blog

Deep-dive articles on hardware engineering, mathematics, and digital signal processing. From RTL design patterns and RISC-V processor internals to DSP theory and computer architecture — written for people who want to understand, not just copy.

Hardware Design DSP Mathematics Architecture
Read Articles →

RTL Lab · What it does

Full HDL Toolchain in One Tab

▶

Verilog Simulation

Run IEEE Verilog and SystemVerilog designs directly on a server-side Icarus Verilog pipeline. Press Ctrl+Enter to simulate and stream console output in real time.

Icarus Verilog
⏣

RTL Schematic Synthesis

Synthesize your HDL into a visual gate-level netlist using Yosys. Toggle between abstract high-level blocks and detailed primitive gates to inspect your logic paths.

Yosys
〰

Interactive Waveforms

Simulation output is automatically parsed from VCD and rendered as a WaveDrom timing diagram. Hover to inspect signal values at any clock cycle. Group signals by module scope.

WaveDrom
⧫

FSM Extraction

Automatically parses your Verilog source to identify Mealy and Moore FSMs and renders them as interactive Cytoscape node graphs. Supports manual layout and auto-arrange.

Cytoscape.js
⊞

FPGA Pin Constraint Generator

Map your top-level module ports to physical FPGA pins in a visual table and export a ready-to-use .xdc file for Xilinx Vivado / Basys 3 boards in one click.

Xilinx XDC
✎

Monaco Editor + Live Linting

Full Monaco Editor (VS Code engine) with Verilog syntax highlighting, live background linting via Verible, auto-format with Shift+Alt+F, and one-click testbench generation.

Verible · Monaco
⚡

AI Hardware Copilot

Context-aware AI assistant powered by Gemini 2.5 Flash. Reads your active source and latest simulation output automatically — no copy-paste needed. Ask for optimizations, bug explanations, or new modules.

Gemini 2.5 Flash
◈

Block Diagram Designer

Canvas-based schematic editor for visually composing module hierarchies. Import modules from the workspace, wire ports, auto-layout by signal flow, and export back to synthesizable top-level Verilog or PNG/SVG.

Canvas API

Under the hood

Technology Stack

Icarus Verilog
Simulation backend
Yosys
RTL synthesis engine
Verible
Lint & auto-format
WaveDrom
Waveform rendering
Monaco Editor
Code editor (VS Code engine)
Cytoscape.js
FSM graph rendering
Node.js + Express
Server & job routing
Gemini 2.5 Flash
AI hardware copilot
BullMQ + Redis
Job queue (synthesis)
MathJax
Math rendering in AI output

Development

What's Been Built

June 2026 — v2.2
Block Designer + AI Context Engine
Canvas-based schematic editor with undo/redo, bookmarks, RTL sync, and Verilog export. AI copilot upgraded with post-simulation context snapshots (waveforms, FSM topology, console logs).
May 2026 — v2.0
Async Job Queue + Hardware Stimulus Board
Replaced synchronous simulation with BullMQ + Redis job queue using spawn() for streaming. Added Hardware Stimulus Board sidebar for port-driven signal injection, Verible linting in Monaco, and multi-file synthesis error attribution.
Early 2026 — v1.5
RTL Tooltips, WaveDrom Grouping, RISC-V CPU
Yosys netlist JSON feeds schematic tooltips. VCD scope hierarchy drives WaveDrom signal grouping. Example library expanded to 13 files including a full RISC-V single-cycle CPU, UART TX, SPI Master, and Sync FIFO.
2025 — v1.0
Initial Launch
Core IDE: Monaco editor, Icarus simulation, Yosys RTL, WaveDrom waveforms, FSM extractor, and FPGA constraint generator shipped as a single-page application.

FAQ

Common Questions

EnggViz RTL Lab is a free, browser-based Verilog IDE and RTL simulator. It integrates Icarus Verilog for simulation, Yosys for RTL synthesis, WaveDrom for waveform visualization, Verible for live linting, and a Monaco-based code editor — all without any installation required.
Visit lab.enggviz.online, write or load a Verilog module and testbench in the editor, then press Ctrl+Enter or click Simulate. The waveform output renders automatically in the Timing tab using WaveDrom.
Yes. The Monaco editor supports SystemVerilog syntax highlighting and live linting via Verible. The Icarus Verilog backend supports a widely-used subset of SystemVerilog constructs including logic, always_ff, always_comb, and packed arrays.
Yes. Click the ⏣ RTL button after writing your Verilog design. EnggViz uses Yosys on the server to synthesize your design into a gate-level or high-level abstract netlist, then renders it as an interactive schematic directly in the browser — no local tools needed.
The FPGA Constraint Generator exports Xilinx XDC files compatible with Vivado and the Basys 3 development board. Map your top-level module ports to physical pins in the visual table and export the file in one click.
Yes. The Silicon AI Copilot is included at no cost. It uses Gemini 2.5 Flash and is context-aware — it automatically reads your active source file and the latest simulation output so you don't need to copy-paste your code to ask questions about it.
EnggViz RTL Lab is a project by EnggViz, an engineering education platform. The backend tools it integrates (Icarus Verilog, Yosys, Verible) are all open-source.

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