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Cache Memory
Simulator
Direct-Mapped · Set-Associative · Fully Associative | FIFO & LRU Replacement
Total Accesses
0
Cache Hits
0
Cache Misses
0
Hit Rate
0%
Address Sequence (comma-separated)
Valid addresses: 0 – 15
Cache Mapping
Direct Mapping
2-Way Set Associative
Fully Associative
Replacement Policy
FIFO — First In, First Out
LRU — Least Recently Used
Run Sequence
Reset
Main Memory — 16 Blocks
Cache Memory — 4 Lines
Waiting for input…
Set / Line
Valid
Tag
Data (Block)
Execution Log
Key Concepts
Hit Rate Formula
Hit Rate = Hits ÷ (Hits + Misses) × 100%
AMAT
AMAT = Hit Time + (Miss Rate × Miss Penalty)
Temporal Locality
Recently accessed data is likely to be needed again — this is why caching works.
Direct Mapping
Index = Address mod Cache_Lines. Each memory block maps to exactly one cache line.